28 CYCLES
INTERPOSER PATH
Model output capture through physical veto assertion.
AVERY CORE KINETICS // EDGE AI INTERPOSER TIMING
Measure the deterministic hardware veto floor independently of probabilistic model execution, with tensor-output capture, register-envelope resolution, and actuator clamp evidence.
28 CYCLES
Model output capture through physical veto assertion.
2.8 µs
A target above 10 MHz qualifies for sub-2.8µs timing.
FP16 / INT8
Safety timing remains independent of model precision.
0 TOKENS
Boolean RTL does not invoke a model or cloud service.
Benchmark the path from NPU or GPU result-ready assertion into the interposer boundary.
Exercise physical and transactional limit violations at the register boundary.
Correlate the offending model output with the final clamp signal and safe-state response.
01 // MODEL READY
Timestamp the customer inference engine’s output-ready signal.
02 // CAPTURE
Latch the proposed command at the VHDL Soft IP.
03 // RESOLVE
Evaluate hardwired domain envelopes without token generation.
04 // VETO
Assert the physical clamp and record cycle-accurate evidence.
The hardware path is benchmarked separately from model inference time. Sub-2.8µs applies only to a 28-cycle interposer implementation closed above 10 MHz on the selected target.